1. Field of the Invention
The present invention relates to technology for non-volatile memory.
2. Description of the Related Art
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electrically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories.
EEPROM and EPROM are non-volatile memories that can be erased and have new data written or “programmed” into their memory cells. Both utilize a floating gate in a transistor structure that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. For a given level charge on the floating gate, there is a corresponding threshold voltage that must be applied to the control gate before the transistor is turned “on” to permit conduction between its source and drain regions.
The floating gate can hold a range of charges and therefore, can be programmed to any threshold voltage level within a threshold voltage window. The size of the threshold voltage window is delimited by the minimum and maximum threshold levels of the device, which in turn correspond to the range of the charges that can be programmed onto the floating gate. The threshold voltage window generally depends on the memory device's characteristics, operating conditions, and history. Each distinct, resolvable threshold voltage level range within the window can, in principle, be used to designate a definite memory state of the cell.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary flash memory device.
A multi-state flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges separated by forbidden ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device.
When programming an EEPROM, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. patent application Ser. No. 10/379,608, titled “Self-Boosting Technique,” filed on Mar. 5, 2003 and U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003, both of which are incorporated herein by reference in their entirety.
As memory cells and circuitry on semiconductor memory chips are scaled down in physical dimension to increase speed and memory density, physical defects that threaten data integrity and chip performance become more prevalent. Among these defects are breaks in word lines, the wires that connect control gates across rows of memory cells in blocks of memory. For example, the breaks in word lines can occur due to heat-induced warping of thin films in the memory die when the memory system is mounted to the circuit board. A break in a word line leads to increased electrical resistance in the word line, which may further lead to an inability to sufficiently charge up the control gate of a memory cell within the time normally allotted for read operations. A failure to sufficiently charge the control gate during read operations might result in errors.